Abstract This paper presents a synthesis method for delay time evaluation in the printed circuit boards based on Timed Hard Petri Nets. For the specification and modeling of the delay time evaluation system, Timed Synchronous Petri Nets (TSPN) are used, which allow conflicts identification and exclusion related to both the processes time synchronization and processes … Continuă lectura Modelling and Synthesis of Printed Circuit Boards Testing Systems based on Timed Hard Petri Nets